1. Field of the Invention
The present invention relates to a data processing device having a DMA (Direct Memory Access) function, and more particularly to a data processing device having a DMA function which is characterized by the interruption processing of a higher-priority interruption request issued during the DMA transfer.
2. Description of the Related Art
In a data processing device having a DMA function, if an interruption request is issued during the DMA transfer, higher-priority interruption processing may be queued until the DMA transfer has been completed, or the DMA transfer may be stopped in order to execute lower-priority interruption processing in some cases. In order to avoid this inconvenience, there has been proposed a data processing technique in the conventional data processing device, in which, with priority established in an interruption request and DMA transfer, the DMA transfer is temporarily halted only in case of priority given to the interruption request over the DMA transfer and the halt of the DMA transfer is released after the interruption processing has been completed.
This kind of the conventional data processing technique is disclosed in, for example, Japanese Patent Publication Laid-Open (Kokai) No. Heisei 5-151143, "An Interruption Processing Method of a computer with a built-in DMA controller". This publication discloses an interruption processing method in which the interruption processing is executed with higher-priority than the DMA transfer only when a higher-priority interruption request than the DMA transfer is issued during the DMA transfer. FIG. 6 is a block diagram showing the constitution of a data processing device for realizing the interruption processing method of this publication.
As illustrated in FIG. 6, the data processing device disclosed in Japanese Patent Publication Laid-Open (Kokai) No. Heisei 5-151143 comprises a DMA controller 101, a CPU 102, a bus arbitration unit (BAU) 103, an interruption controller 104, a comparator 106 for making a comparison between the priority put on an interruption request and the priority established in a register 105 of the DMA controller 101, and a comparator 108 for making a comparison between the priority put on an interruption request and the priority established in a register 107 of the CPU 102. When the priority "a" of an interruption request supplied from the interruption controller 104 is higher than the priority "b" of the DMA controller 101, a signal "c" for temporarily halting the DMA transfer is supplied and the bus-using right is returned to the CPU 102, to thereby execute the interruption processing by priority. Thereafter, a DMA halt releasing signal "d" is supplied from the CPU 102 at the termination of the interruption processing, to resume the DMA transfer.
The above-mentioned conventional data processing device having a DMA function takes much time to stop the DMA transfer disadvantageously when a higher-priority interruption request than the DMA transfer is issued and the DMA transfer is not temporarily halted but canceled, in other words, when the state of a sequencer for the DMA transfer control is returned to the reset state and the bus-using right is abandoned. This is why predetermined processing such as to initialize the DMA controller is necessary in case of stopping the DMA transfer, and why the execution program of interruption processing must include a program for executing the predetermined processing.